Fault-tolerant Method and Simulation of Heterogeneous Multi-core Processor Based on Speculative Mechanism

doi:10.16182/j.issn1004731x.joss.19-FZ0346

Abstract

Abstract: Heterogeneous multicore is one of the important branches of processors,but they are still faced with frequent transient failures. TMR(Triple mode redundancy) is the main method to solve transient faults, which has the characteristics of low efficiency and high power consumption, a high-performance Fault-Tolerant Scheduling Algorithm with Speculative mechanism(FTSAS) is proposed. Each heterogeneous core can execute tasks independently, the state values of the first completed core are recorded, and the first completed core continues to perform the next task with forward speculative method. The results are compared by backward core, the majority consensus principle is adopted to ensure the reliability of the system. The simulation results show the average performance of the FTSAS is improved by 12.9% compared with state-of-the-art methods. When 200 errors are injected, the FTSAS has a similar fault-tolerant effect, however, FTSAS can achieve 11.4% average efficiency improvement and 15.8% average power consumption decrement.

Key words: Heterogeneous multicore, Processor, Speculative mechanism, fault tolerance, Scheduling

CLC Number:

TP391.7

Yu Shigan, Tang Zhimin, Ye Xiaochun, Fan Dongrui. Fault-tolerant Method and Simulation of Heterogeneous Multi-core Processor Based on Speculative Mechanism[J]. Journal of System Simulation, 2019, 31(12): 2685-2695.

References

[1] McNairy C. Exascale fault tolerance challenge and approaches[C]. IEEE International Reliability Physics Symposium. Burlingame,USA: IEEE, 2018: 3C.4.1-10.
[2] Chen J, John L K.Efficient Program Scheduling for Heterogeneous Multicore Processors[C]. 46^th ACM/ IEEE Design Automation Conference. San Francisco, USA: IEEE, 2009: 927-930.
[3] Baital K, Chakrabarti A.Dynamic Scheduling of Real- Time Tasks in Heterogeneous Multicore Systems[J]. IEEE Embedded Systems Letters (S1943-0671), 2019, 11(1): 29-32.
[4] Greenhalgh P Big. LITTLE processing with ARM Cortex -A15&Cortex-A7. [EB/OL]. [2018-09]. http://www. arm.com.
[5] NVIDIA Corporation. Variable SMP-a multi-core CPU architecture for low power and high performance[EB/OL]. http://www.Nvidia.com. 2018.
[6] Chitlur N, Srinivasa G, Hahn S, et al.QuickIA: Exploring heterogeneous architectures on real prototypes[C]. IEEE International Symposium on High-Performance Computer Architecture (HPCA). New Orleans, USA: IEEE, 2012: 1-8.
[7] 海思麒麟980参数[EB/OL]. [2019-04-01].https: // baike. baidu.com.
Parameters of the kirin 980[EB/OL]. [2019-04-01].https: // baike.baidu. com.
[8] Naithani A, Eyerman S, Eeckhout L.Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors[J]. IEEE Transactions on Computers (S1557-9956), 2018, 67(6): 830-846.
[9] Raparti V Y, Kapadia N, Pasricha S.CHARM: A check point-based resource manage-ment framework for reliable multicore computing in the dark silicon era[C]. IEEE International Conference on Computer Design (ICCD). Scottsdale, USA: IEEE, 2016: 201-208.
[10] Karlsson J, Liden P, Dahlgren P, et al.Using Heavy-ion Radiation to Validate Fault Handling Mechanisms[J]. IEEE Micro (S1937-4143), 1994, 14(1): 8-23.
[11] Lim H, Kim T, Lee D, et al.LARECD: Low area over- head and reliable error correction DMR architecture[C]. International SoC Design Conference. Seoul, South Korea: IEEE, 2018: 27-28.
[12] Zheng P, Zheng Q, Zeng Z.The Signal Design and Simulation of Triple Modular Redundant (TMR) Computer[C]. International Conference on Cybernetics and Intelligent Systems (CIS) and Conference on Robotics, Auto-mation and Mechatronics (RAM). Ningbo, China: IEEE, 2017: 758-762.
[13] 孙晓星. 面向方面的软件容错模型设计与分析技术 [D]. 上海: 华东理工大学, 2012.
Sun Xiaoxing.Aspect-oriented Modeling and Analysis Techniques for Software Fault Tolerance[D]. Shanghai: East China University of Science and Technology, 2012.
[14] Abate F, Sterpone L, Lisboa C A, et al.New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA Embedded Processors[J]. IEEE Transactions on Nuclear Science (S1558-1578), 2009, 56(4): 1992-2000.
[15] Roy A, Aydin H.Energy-efficient primary/backup scheduling techniques for heterogeneous multicore systems[C]. International Green and Sustainable Computing Conference. Orlando, USA: IEEE, 2017: 1-8.
[16] Ning L, Yao W, Ni J, et al.Fault Tolerance CMP Architecture based on SMT Technology[C]. International Multi-Symposiums on Computer and Computational Sciences. Iowa City, USA: IEEE, 2007: 425-429.
[17] 贾佳, 杨学军, 马亚青. 静态分析面向异构系统的应用级Checkpoint设置问题[J]. 软件学报, 2013, 24(6): 1361-1375.
Jia Jia, Yang Xuejun, Ma Yaqing.Static analysis for placement of application-level Checkpoints on heterogeneous system[J]. Chinese Journal of Software, 2013, 24(6): 1361-1375.
[18] 李祖松, 许先超, 胡伟武, 等. 龙芯2号处理器的同时多线程设计[J]. 计算机学报, 2009, 32(11): 2265-2273.
Li Zusong, Xu Xianchao, Hu Weiwu, et al.Design of the Simultaneous Multithreading Godson-2 Processor[J]. Chinese Journal of Computers, 2009, 32(11): 2265-2273.
[19] 贾佳, 杨学军, 李志凌. 一种基于冗余线程的GPU多副本容错技术[J]. 计算机研究与发展, 2013, 50(7): 1551-1562.
Jia Jia, Yang Xuejun, Li Zhiling.A Redundancy- Multithread-Based Multiple GPU Copies Fault- Tolerance Technique[J]. Chinese Journal of Computer Research and Development, 2013, 50(7): 1551-1562.
[20] 曹英. 大数据环境下Hadoop性能优化的研究[D]. 大连: 大连海事大学, 2013.
Cao Ying.Research of Performance Optimization of Hadoop in BigData[D]. Dalian: Dalian Maritime University, 2013.
[21] 陆志伟. 航空器无冲突4D航迹推测与生成[D]. 南京: 南京航空航天大学, 2012.
Lu Zhiwei.The Conflict-free 4D Trajectory Prediction and Generation for Aircrafts[D]. Nanjing: Nanjing University of Aeronautics and Astronautics, 2012.
[22] 王丽华. 计算机容错系统的体系结构与安全性研究[D]. 成都: 西南交通大学, 2002.
Wang Lihua.The Research About the Architecture and Safety of the Computer Fault-tolerant System[D]. Chengdu: Southwest Jiaotong University, 2002.
[23] 谢国琪, 李仁发, 刘琳, 等. 异构分布式DAG可靠性模型与容错算法[J]. 计算机学报, 2013, 36(10): 2020-2033.
Xie Guoqi, Li Renfa, Liu Lin, et al.DAG Reliability Model and Fault-Tolerant Algorithm for Heterogeneous Distributed Systems[J]. Chinese Journal of computers, 2013, 36(10): 2020-2033.
[24] Benoit A, Hakem M, Robert Y.Fault tolerant scheduling of precedence task graphs on heterogeneous platforms[C]. IEEE International Symposium on Parallel and Distributed Processing. Miami, USA: IEEE, 2008: 1-8.
[25] Benoit A, Hakem M, Robert Y.Contention Awareness and Fault-tolerant Scheduling for Precedence Constrained Tasks in Heterogeneous Systems[J]. Parallel Computing (S0167-8191), 2009, 35(2): 83-108.
[26] 付剑. 星载计算机硬件容错设计与可靠性分析[D]. 长沙: 国防科技大学, 2009.
Fu Jian.The hardware Fault-tolerant Design and Reliability Analysis of On Board Computer[D]. Changsha: National University of Defense Technology, 2009.
[27] Xu J, Zhu Y, Ni J.A Simulator for Multicore Processor Micro-architecture Featuring Intercore Communication, Power and Thermal Behavior[C]. International Conference on Embedded Software and Systems Symposium. Sichuan China: IEEE, 2008: 237-242.
[28] Simplescalar LLC to serve and project[EB/OL]. [2018-09-20]. http:// www.simple scalar.com.
[29] 张福新, 章隆兵, 胡伟武. 基于Simplescalar的龙芯CPU模拟器Sim-Godson[J]. 计算机学报, 2007, 30(1): 68-73.
Zhang Fuxin, Zhang Longbin, Hu Weiwu.Sim-Godson: A Godson Processor Simulator Based on SimpleScalar[J]. Chinese Journal of Computers, 2007, 30(1): 68-73.
[30] 陈文智, 姜振宇, 吴帆. 基于MIPS体系的扩展指令融合技术[J]. 计算机学报, 2008, 31(11): 1888-1897.
Chen Wenzhi, Jiang Zhenyu, Wu Fan.Instruction Fusion Technology for the MIPS[J]. Chinese Journal of Computers, 2008, 31(11): 1888-1897.
[31] Luo Y, Packirisamy V, Hsu W.Energy efficient speculative threads: Dynamic thread allocation in same-ISA heterogeneous multicore systems[C]. Inter-national Conference on Parallel Architectures and Compilation Techniques. Vienna, Austria: IEEE, 2010: 453-464.
[32] 王健, 孙建伶, 王新宇, 等. 容错多处理机中一种高效的实时调度算法[J]. 软件学报, 2009, 20(10): 2628-2636.
Wang Jian, Sun Jianling, Wang Xinyu, et al.Efficient Scheduling Algorithm for Hard Real-Time Tasks in Primary-backup Based Multiprocessor Systems[J]. Chinese Journal of Software, 2009, 20(10): 2628-2636.
[33] Brooks D, Tiwari V, Martonosi M.Wattch: A framework for Architectural-Level Power Analysis and Optimi- zation[C]. Proceedings of the 27^th Annual International Symposium on Computer Architecture. Vancouver, BC, Canada: IEEE, 2000: 83-94.
[34] 倪俊杰. 基于SimpleScalar的性能和功耗分析多核模拟器[D]. 上海: 上海交通大学, 2008.
Ni Junjie.A Multiprocessor Simulator with Power Analysis Based on SimpleScalar[D]. Shanghai: Shanghai Jiao Tong University, 2008.
[35] 郑凯. 对数据在异构多核处理器模拟器中进行任务划分的研究[D]. 上海: 上海交通大学, 2008.
Zheng Kai.Evaluation of Partitioning Methods for Application on a Heterogeneous Multicore Processor Simulator[D]. Shanghai: Shanghai Jiao Tong University, 2008.