High Performance Fault-tolerant Scheduling Method and Simulation for Heterogeneous Multicore

doi:10.16182/j.issn1004731x.joss.201811020

Abstract

Abstract: To deal with the problem of low performance and high power consumption when solving the transient fault of the processor with three mode redundancy (TMR), a task execution algorithm for heterogeneous multicore considering fault tolerant (TEAHFT) is proposed. The tasks to be executed are divided into sensitive tasks and fault-tolerant tasks. The sensitive tasks are executed in a TMR mode, and the fault-tolerant tasks are executed in a competitive scheduling mode. The task will be rerun in TMR method if the results of the fault-tolerant tasks do not meet the reliability threshold. The simulation experimental results show that TEAHFT achieves a 16.4% average efficiency improvement over TMR and PB methods when running test cases. TEAHFT, TMR and PB have similar fault-tolerant results, but TEAHFT’s average execution efficiency has increased by 14.1% and the power consumption decreased by 22.1% when 100 errors were injected.

Key words: TMR, heterogeneous multicore, competitive mechanism, fault tolerance, simulation

CLC Number:

TP391.7

Yu Shigan, Tang Zhimin, Ye Xiaochun, Zhang Zhimin. High Performance Fault-tolerant Scheduling Method and Simulation for Heterogeneous Multicore[J]. Journal of System Simulation, 2018, 30(11): 4210-4220.

References

[1] Jian Chen, Lizy K John.Efficient Program Scheduling for Heterogeneous Multicore Processors[C]. 46th ACM/IEEE Design Automation Conference, San Francisco, CA, USA: IEEE, 2009: 927-930.
[2] 易娟. 面向多核处理器系统的可靠性与能耗优化调度研究[D]. 重庆: 重庆大学, 2016.
Yi Juan.Multiprocessor Systems Scheduling for the Optimization of Reliability and Energy Consumption[D]. Chongqing: Chongqing University, 2016.
[3] 傅忠传, 陈红松, 崔刚, 等. 处理器容错技术研究与展望[J]. 计算机研究与发展, 2007, 44(1): 154-160.
Fu Zhongchuan, Chen Hongsong, Cui Gang, et al.Processor Fault-Tolerance Technology Research and Prospect[J]. Journal of Computer Research and Development, 2007, 44(1): 154-160.
[4] J Karlsson, P Liden, P Dahlgren, et al.Using Heavy-ion Radiation to Validate Faulthandling Mechanisms[J]. IEEE Micro (S0272-1732), 1994, 14(1): 8-23.
[5] S Mukherjee.Architecture Design for Soft Errors[M]. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc, 2008.
[6] A Ienis.Building Dependable Systems: How to Keep Up with Complexity[C]. International Conference on Fault- tolerant Computing, 1995: 4-14.
[7] 陆阳, 王强, 张本宏, 等. 计算机容错技术研究[J]. 计算机工程, 2010, 36(13): 230-235.
LU Yang, WANG Qiang, ZHANG Ben-hong, et al.Research on Fault-tolerant Technology for Computer System[J]. Computer Engineering, 2010, 36(13): 230-235.
[8] Xun Jian, Rakesh Kumar.ECC Parity: A Technique for Efficient Memory Error Resilience for Multi- Channel Memory Systems[C]. Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis. New Orleans, LA, USA, 2014: 1035-1046.
[9] John M Bird, Michael K Peters, Travis Z Fullem, et al.Neutron Induced Single Event Upset (SEU) Testing of Commercial Memory Devices with Embedded Error Correction Codes (ECC)[C]. IEEE Radiation Effects Data Workshop(REDW), New Orleans, LA, USA: IEEE, 2017: 17-21.
[10] Omer Subasi, Osman Unsal, Jesus Labarta, et al.CRC-Based Memory Reliability for Task-Parallel HPC Application[C]. International Parallel and Distributed Processing Symposium (IPDPS), 2016: 1101-1112.
[11] Evgeny Tsimbalo, Xenofon Fafoutis, Robert J Piechocki.CRC Error Correction in IoT Applications[J]. IEEE Transactions on Industrial Informatics (S1551-3203), 2017, 13(1): 361-369.
[12] Yu-Peng Hu, Nong Xiao, Xiao-Fan Liu.An Elastic Error Correction Code Technique for NAND Flash-Based Consumer Electronic Devices[J]. IEEE Transactions on Consumer Electronics (S0098-3063), 2013, 59(1): 1-8.
[13] Anjana Balachandran, Nandeesh Veeranna, Benjamin, et al. On Time Redundancy of Fault Tolerant C-Based MPSoCs[C]. IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, 2016: 631-636.
[14] Dmitry Burlyaev, Pascal Fradet, Alain Girault.Time- Redundancy Transformations for Adaptive Fault-Tolerant Ciruits[C]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2015: 1-8.
[15] Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, et al.Fine-Grained Checkpoint Recovery for Application- Specific Instruction-Set Processors[J]. IEEE Transactions on Computers(S0018-9340), 2017, 66(4): 647-660.
[16] Nosayba El-Sayed, Bianca Schroeder.Understanding Practical Tradeoffs in HPC Checkpoint-Scheduling Policies[J]. IEEE Transactions on Dependable and Secure Computing (S1545-5971), 2018, 15(2): 336-350.
[17] Pan Zheng, Qi Zheng, Zhankui Zeng.The Signal Integrity Design and Simulation of Triple Modular Redundant (TMR) Computer[C]. IEEE International Conference on Cybernetics and Intelligent Systems (CIS) and IEEE Conference on Robotics, Automation and Mechatronics (RAM), Ningbo, China, 2017: 758-762.
[18] Julen Gomez-Cornejo, Aitzol Zuloaga, Uli Kretzs chmar, et al. Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor[C]. 39th Annual Conference of the IEEE Industrial Electronics Society. Vienna, Austria, 2013: 2261-2266.
[19] Luca Sterpone, Luca Boragno.Analysis of Radiation- Induced Cross Domain Errors in TMR Aarchitectures on SRAM-Based FPGAs[C]. 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), Thessaloniki, Greece, 2017: 174-179.
[20] Jyothish Soman, Timothy M Jones.High performance fault tolerance through predictive instruction re-execution[C]. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Cambridge, UK, 2017: 1-4.
[21] Wangyuan Zhang, Xin Fu, Tao Li, et al.An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures[C]. IEEE International Symposium on Performance Analysis of Systems & Software, San Jose, CA, USA, 2007:169-178.
[22] Jie Yin, Jianhui Jiang.Design and analysis of an asynchronous checkpoint-based redundant multithreading architecture[C]. IEEE World Automation Congress, Puerto Vallarta, Mexico, 2012: 519-523.
[23] Jing Wei-peng, Liu Ya-qiu, Wu Qu.Fault-Tolerant Task Scheduling in Multiprocessor Systems Based on Primary-backup Scheme[C]. 3rd International Symposium on Systems and Control in Aeronautics and Astronautics, Harbin, China, 2010: 670-675.
[24] J F Wakerly.Transient Failures in Triple Modular Redundancy Systems with Sequential Modules[J]. IEEE Transactions on Computers (S0018-9340), 1975, 24(5): 570-573.
[25] 贾佳, 杨学军, 李志凌. 一种基于冗余线程的GPU多副本容错技术[J]. 计算机研究与发展, 2013, 50(7): 1551-1562.
Jia Jia, Yang Xuejun, Li Zhiling.A Redundancy-Multi thread-Based Multiple GPU Copies Fault-Tolerance Technique[J]. Journal of Computer Research and Development, 2013, 50(7): 1551-1562.
[26] Xiaoxuan She, N Li. Reducing Critical Configuration Bits via Partial TMR for SEU Mitigation in FPGAs[J]. IEEE Transactions on Nuclear Science (S0018-9499), 2017, 64(10): 2626-2632.
[27] Zhuoran Zhao, Dimitris Agiakatsikas, Nguyen T H Nguyen. Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems[C]. International Conference on Field-Programmable Technology (FPT), Xi'an, China, 2016: 101-108.
[28] A J Sanchez-Clemente, L Entrena, M García-Valderas. Partial TMR in FPGAs Using Approximate Logic Circuits[J]. IEEE Transactions on Nuclear Science (S0018- 9499), 2016, 63(4): 2233-2240.
[29] Hashem H Najaf-abadi, Eric Rotenberg. Architectural Contesting[C]. IEEE 15th International Symposium on High Performance Computer Architecture, Raleigh, NC, USA, 2009: 189-200.
[30] J Xu, Y Zhu, J Ni, et al.A Simulator for Multicore Processor Micro-architecture Featuring Inter-core Communication, Power and Thermal Behavior[C]. International Conference on Embedded Software and Systems Symposium, 2008: 237-242.
[31] Simplescalar LLC. Simplescalar LLC to serve and project [EB/OL]. [2018-05-30]. http://www.simplescalar. com.
[32] Chunho Lee, M Potkonjak, W H Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communication Systems[C]. Proceedings of 30th Annual International Symposium on Micro- architecture, Research Triangle Park, NC, USA,1997: 330-335.
[33] T Austin, E Larson, E Dan.SimpleScalar: An Infrastruc- ture for Computer System Modeling[J]. Computer (S0018-9162), 2002, 35(2): 59-67.
[34] 王健, 孙建伶, 王新宇, 等. 容错多处理机中一种高效的实时调度算法[J]. 软件学报, 2009, 20(10): 2628-2636.
J Wang, J L Sun, X Y Wang, et al.Efficient Scheduling Algorithm for Hard Real-Time Tasks in Primary-backup Based Multiprocessor Systems[J]. Journal of Software, 2009, 20(10): 2628-2636.
[35] Brooks D, Martonosi M.Wattch: A framework for Architectural-Level Power Analysis and Optimization[C]. the 27th Annual International Symposium on Computer Architecture, Vancouver, BC, Canada. 2000: 83-94.
[36] 郑凯. 对数据在异构多核处理器模拟器中进行任务划分的研究[D]. 上海: 上海交通大学, 2008.
Zheng kai. Evaluation of Partitioning Methods for Application on a Heterogeneous Multicore Processor Simulator [D]. Shanghai: Shanghai jiaotong University, 2008.