Design and Implementation of Reconfigurable Video Array Processor Test Platform

doi:10.16182/j.issn1004731x.joss.18-0542

Abstract

Abstract: Aiming at the design requirements of the reconfigurable video array processor and the problem of traditional method testing the video codec system with slow speed, low precision and poor observability. A Qt-based user interface is developed, and a hardware-software co-testing platform based on FPGA is designed and implemented. The platform realizes the data transmission and image reproduction based on the software simulation on the PC side, and the parallel mapping of the video encoding and decoding algorithms based on the reconfigurable video array processor on the FPGA side. The experiment results show that the data can be transmitted correctly between FPGA and PC when the working frequency of the platform is 100 MHz, and the replacement demand of the different test cases can be satisfied when the algorithm is tested, and the experiment has a good observability.

Key words: testing platform, hardware and software collaboration, user interface, video codec, reconfigurable video array processor

CLC Number:

TP391.9

Jiang Lin, He Feilong, Shan Rui, Wang Shuai, Wu Haoyue, Wu Xin. Design and Implementation of Reconfigurable Video Array Processor Test Platform[J]. Journal of System Simulation, 2020, 32(5): 792-800.

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