HDRT实时仿真系统设计与实现

doi:10.16182/j.issn1004731x.joss.25-0932

摘要/Abstract

摘要：

针对电力电子等大规模复杂系统的实时仿真需求，研发了HDRT(hidden dragon real time)仿真系统。基于一种资源独占式实时化方案保证仿真任务的严格时间约束，支持从秒级到百纳秒级的定步长、多速率仿真。采用CPU-FPGA(field programmable gate array)混合架构加速计算。系统可以利用多台仿真机进行并行仿真，并通过专用PCIe交换机实现仿真机间微秒级实时数据交互。单台仿真机可通过I/O接口设备进行扩展，最大支持1 500路以上实时模拟信号或3 000路以上实时数字信号的输入或输出。测试结果表明：HDRT仿真系统中单个I/O接口设备的同步时间仅为40 ns，I/O接口设备间具有快速同步的特点；主从仿真任务实际仿真步长的最大抖动分别不超过180 ns和400 ns；基于实际仿真模型进行测试，结果证明了HDRT仿真系统具备大型复杂系统的实时仿真能力。

关键词: 实时系统, 半实物仿真, 并行计算, 同步, 系统设计

Abstract:

In view of the real-time simulation requirements of large-scale complex systems such as power electronics, a hidden dragon real-time(HDRT) simulation system was developed. The strict time constraints of simulation tasks were guaranteed based on a resource-dedicated real-time scheme, supporting fixed-step and multi-rate simulations from the second level to the hundred-nanosecond level. A hybrid CPU-field programmable gate array(FPGA) architecture was adopted to accelerate computation. The system could utilize multiple simulators for parallel simulation and realized microsecond-level real-time data interaction between simulators through a dedicated PCIe switch. A single simulator could be expanded through I/O interface equipment, supporting a maximum input or output of more than 1 500 channels of real-time analog signals or more than 3 000 channels of real-time digital signals. Test results indicate that the synchronization time of a single I/O interface equipment in the HDRT simulation system is only 40 ns, indicating the characteristic of fast synchronization among I/O interface equipment; the maximum jitters of the actual simulation steps of the master and slave simulation tasks do not exceed 180 ns and 400 ns, respectively; based on tests of actual simulation models, the results demonstrate that the HDRT simulation system possesses the real-time simulation capability for large-scale complex systems.

Key words: real-time system, hardware-in-the-loop simulation, parallel computation, synchronization, system design

中图分类号:

TP399

郑会吉,汪光森,柳青等 . HDRT实时仿真系统设计与实现[J]. 系统仿真学报, 2026, 38(8): 2364-2378.

Zheng Huiji,Wang Guangsen,Liu Qing,et al . Design and Implementation of HDRT Real-time Simulation System[J]. Journal of System Simulation, 2026, 38(8): 2364-2378.

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目录	命令	描述
内核编译选项	CONFIG_NO_HZ=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_FULL=y	支持nohz_full模式，结合内核启动参数nohz_full=core_list使用，关闭指定实时CPU核心空闲和单个任务运行时的tick中断
	CONFIG_CPU_ISOLATION=y	支持CPU隔离，结合内核启动参数isolcpus=core_list使用，将指定CPU核心从调度算法中移除
	CONFIG_PREEMPT=y	使能抢占式内核(PREEMPT_RT)
内核启动参数	isolcpus=core_list	将指定CPU核心从调度算法中移除
	nohz_full=core_list	关闭指定实时CPU核心空闲和单个任务运行时的tick中断
	tsc=reliable	避免TSC时钟校准功能导致的tcik中断
	mce=off	避免机器检查异常功能导致的tick中断
用户层工具	echo 1>/proc/irq/*/smp_affinity	设置IRQ亲和性到指定核心
	taskset-pc 0/proc/*	将系统非实时进程迁移到非实时CPU核心
	echo performance>/sys/devices/system/cpu/cpu*/cpufreq/scaling_governor	设置CPU频率调节器为性能模式，避免造成性能抖动
	echo-1>/proc/sys/kernel/sched_rt_runtime_us	避免限制实时核心的CPU时间片导致tick中断
	echo 0>/sys/devices/system/cpu//online echo 1>/sys/devices/system/cpu//online	重启实时CPU，通过热插拔CPU，强制将该CPU上的部分定时器软中断等迁移到非实时CPU上^[21]

采样工具	显示位置及格式	采样方式	采样频率限制因素
上位机管理软件	上位机文件或图像	HDTarget实时任务缓存记录，非实时任务通过UDP上传上位机	网络和图像渲染速度
HDWriteFile模块	HDTarget文件	HDTarget实时任务缓存记录，非实时任务写入本地文件	内存写入文件速度
Get_Signal模块	上位机Simulink信号	HDTarget实时任务缓存记录，上位机Simulink模块通过TCP读取	网络与Simulink数据处理速度

监视工具	(事件)数据来源	监视周期	监视内容	精度	中断定位
imon	/proc/interrupts和SMI计数器	imon命令启动后	硬中断和SMI中断个数	s	CPU编号、中断类型
pmu监视器	硬件性能计数器	仿真过程中	硬中断个数和其他性能事件	ms	CPU编号
内核监视器	独占模式丢失监视补丁	仿真开始前、仿真过程中、仿真结束后	含硬中断和信号内陷等广义中断	μs	CPU编号、中断类型、调用栈

HDIO数量	时长
1	40
2	96
3	144

HDTarget	子系统	仿真步长/μs	最大仿真步长抖动/ns
Ⅰ	1(从)	75	249
	2(从)	100	271
	3(从)	100	279
	4(从)	100	281
	5(从)	25	179
	6(主)	25	172
Ⅱ	1(从)	25	269
	2(从)	25	356
	3(从)	25	378
	4(主)	25	169
Ⅲ	1(从)	25	377
	2(从)	100	250
	3(从)	25	347
	4(从)	25	318
	5(主)	25	170