系统仿真学报 ›› 2018, Vol. 30 ›› Issue (11): 4210-4220.doi: 10.16182/j.issn1004731x.joss.201811020

• 仿真系统与技术 • 上一篇    下一篇

异构多核的一种高性能容错调度方法与仿真

余世干1,2,3, 唐志敏1,2, 叶笑春1,2, 张志敏1,2   

  1. 1.中国科学院计算技术研究所计算机体系结构国家重点实验室,北京 100190;
    2.中国科学院大学计算机控制与工程学院,北京 100049;
    3.阜阳师范学院信息工程学院,安徽 阜阳 236041
  • 收稿日期:2018-05-30 修回日期:2018-07-30 发布日期:2019-01-04
  • 作者简介:余世干(1982-), 男, 安徽定远, 博士生, 副教授, 研究方向为计算机体系结构与容错, 并行处理。
  • 基金资助:
    国家重点研发计划(2018YFB1003500),国家自然科学基金(61332009,61521092),安徽省高校自然科学重点项目(KJ2017A837,KJ2018A0669)

High Performance Fault-tolerant Scheduling Method and Simulation for Heterogeneous Multicore

Yu Shigan1,2,3, Tang Zhimin1,2, Ye Xiaochun1,2, Zhang Zhimin1,2   

  1. 1.State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;
    2.School of Computer and Control Engineering, University of Chinese Academy of Sciences, Being 100049, China;
    3. Information Engineering college, Fuyang Normal University, Fuyang 236041, China
  • Received:2018-05-30 Revised:2018-07-30 Published:2019-01-04

摘要: 针对TMR(Three mode redundancy)在解决处理器瞬态故障时存在性能低下,功耗较高等问题,提出了一种考虑容错的面向异构多核的调度方法TEAHFT,把任务划分为敏感性任务和具有容错性任务,其中敏感性任务以TMR方式执行,具有容错性任务以竞争调度方式执行,如果未达到可靠性阈值的任务,则以TMR方式重新执行以满足系统可靠性要求。仿真实验表明,执行测试用例,TEAHFT比TMR,PB方法的性能平均提高了16.4%,注入100个错误时,TEAHFT与TMR,PB具有相近的容错效果,但是TEAHFT平均执行效率提升了14.1%,功耗平均降低了22.1%。

关键词: 三模冗余, 异构多核, 竞争机制, 容错, 仿真

Abstract: To deal with the problem of low performance and high power consumption when solving the transient fault of the processor with three mode redundancy (TMR), a task execution algorithm for heterogeneous multicore considering fault tolerant (TEAHFT) is proposed. The tasks to be executed are divided into sensitive tasks and fault-tolerant tasks. The sensitive tasks are executed in a TMR mode, and the fault-tolerant tasks are executed in a competitive scheduling mode. The task will be rerun in TMR method if the results of the fault-tolerant tasks do not meet the reliability threshold. The simulation experimental results show that TEAHFT achieves a 16.4% average efficiency improvement over TMR and PB methods when running test cases. TEAHFT, TMR and PB have similar fault-tolerant results, but TEAHFT’s average execution efficiency has increased by 14.1% and the power consumption decreased by 22.1% when 100 errors were injected.

Key words: TMR, heterogeneous multicore, competitive mechanism, fault tolerance, simulation

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